The present invention relates generally to integrated circuits. More particularly, the present invention relates to stacked integrated circuits.
Integrated circuits form the basis for many electronic systems. Essentially, an integrated circuit (IC) includes a vast number of transistors and other circuit elements that are formed on a single semiconductor wafer or chip and are interconnected to implement a desired function. The complexity of these integrated circuits requires the use of an ever increasing number of linked transistors and other circuit elements. As the number of transistors involved increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices that are fabricated on the same and on different wafers or chips. It is an objective in the semiconductor industry to construct transistors that occupy less surface area on the silicon chip or die.
Many electronic systems are created through the use of a variety of different ICs, each of which performs one or more specific functions. For example, computer systems include at least one microprocessor and a number of memory chips. Conventionally, each of these ICs is formed on a separate wafer or chip, packaged independently and interconnected on, for example, a printed circuit board.
As IC technology progresses, there is a growing desire for a xe2x80x9csystem on a chip,xe2x80x9d in which the functionality of all of the ICs of the system are packaged together without a conventional printed circuit board. Ideally, such a computing system would be fabricated with all the necessary ICs on one wafer, as compared with conventional methods of fabricating many chips of different functions and packaging them to form a complete system. Such a structure would greatly improve IC performance and provide higher bandwidth.
In practice, however, it is very difficult with conventional technology to implement a truly high-performance xe2x80x9csystem on a chipxe2x80x9d because of the vastly different fabrication processes and different manufacturing yields for the logic and memory circuits. As a compromise, various xe2x80x9csystem modulesxe2x80x9d have been introduced that electrically connect and package IC devices that are fabricated on the same or on different semiconductor wafers. Initially, system modules were created by simply stacking two semiconductor chips, e.g., a logic chip and a memory chip, one on top of the other in an arrangement commonly referred to as chip-on-chip (COC) structure. Chip-on-chip structures most commonly use micro bump bonding (MBB) technology to electrically connect the working surfaces of two chips. Several problems, however, remain inherent with this design structure. For example, this approach is limited in the number of chips that can be interconnected as part of the system module.
Several approaches to assembling memory chips to form a high-density memory cube have been explored. In one technique, stacked chips are vertically interconnected using gold wire bonding. The chips are epoxy bonded to tapes, and the wires between the chip and the tape are trimmed with a diamond saw. For parallel computing applications, a central processing unit (CPU) can be surrounded by cache memory chips. Each memory die is located in its own cavity on the package substrate, which is formed from low-temperature co-fired ceramic (LTCC). Another approach uses a three-dimensional vertical module structure that consists of single chip modules that are constructed from mass-produced memory devices. A multi-chip architecture for use in a reduced instruction set computer (RISC) consists of a base substrate having a deposited organic film on a laminated printed circuit board, a glass-ceramic-based organic thin film multilayer build-up chip scale package (CSP), and a glass-ceramic three-dimensional memory module. Still another approach integrates both COC and chip-on-board (COB) architectures into a single three-dimensional package.
Other proposals have been developed for interconnecting a number of chips in a stack to form a system module. However, these modules suffer from additional problems. For example, some modules use chip carriers that make the packaging bulky. Further, others use wire bonding that gives rise to stray inductances that interfere with the operation of the system module.
Another issue of particular importance with respect to stacked IC design is power consumption. In the context of limited-power environments, such as portable devices, power consumption considerations are especially critical. To reduce power consumption, efforts have been made to reduce the operating voltage of devices. Reducing the operating voltage of analog circuits, however, reduces their dynamic range and degrades high-frequency characteristics. One solution to this problem is to use large scale integrated circuits (LSIs) that have multiple operating voltages. For example, according to one conventional approach, power supply components, such as high-efficiency DC-to-DC converters, are integrated into the same chip so as to provide multiple operating voltages, such as a low voltage core for use with digital circuitry and a higher voltage rim for devices that use a higher operating voltage.
Reducing the size of the DC-to-DC converters is desirable to conserve device space for other components. A typical DC-to-DC converter includes semiconductor devices, magnetic components, e.g., transformers and inductors, resistors, and capacitors. FIG. 11 depicts a conventional DC-to-DC converter 1100 consisting of a silicon substrate 1102, on which a rectifier 1104, a capacitor 1106, a switch 1108, and control circuitry are formed in a semiconductor device region 1112. A thin-film inductor 1114 is formed on the silicon substrate 1102 outside of the semiconductor device region 1112.
An effective way of reducing the size of a DC-to-DC converter is to reduce the size of the magnetic components in the converter. This approach increases reliability and operating frequency, allowing for a reduced number of parts and a shortened length of wire bonding. As a result, the power supply component can be formed with a smaller size. Power dissipation is also reduced.
A single-chip DC-to-DC converter involves integration of semiconductor devices and magnetic devices on a single chip. One approach to realizing this goal is to fabricate a thin-film magnetic component on a silicon substrate, thus allowing semiconductor devices based on silicon technology to be integrated with magnetic components. The use of planar magnetic elements as inductors or transformers is known in the art. FIGS. 12 and 13 respectively depict a schematic diagram and a circuit diagram of a planar microtransformer 1200 with monolithically integrated rectifier diodes 1202 on a silicon substrate 1204 fabricated using a dry process. The microtransformer 1200 can be formed using, for example, thin film deposition using chemical vapor deposition or sputtering and ion beam etching or reactive ion etching. A transformer 1206 is formed by a copper primary coil 1208 and a copper secondary coil 1210 wrapped around a transformer core 1212 of a ternary alloy of CoZrRe.
The fabrication process itself introduces certain obstacles to improving the efficiency of thin-film magnetic devices. For example, their inductance or Q factor should be increased, and their equivalent resistance should be reduced. For applications in which these characteristics are critical, inductors having larger dimensions can be fabricated by micromachining or fabricated on other, smaller, silicon wafers and mounted on the power supply integrated circuit die.
Accordingly, it is desirable to develop an improved structure and method for interconnecting ICs of different types, including those implementing digital, analog, and RF functions, on separate chips or wafers in a system module.
The above mentioned problems with ICs and other problems are addressed by the present invention and will be understood by reading and studying the following specification. System modules are described that include a stack of interconnected semiconductor chips, wafers, or dies. The semiconductor dies are interconnected by micro bump bonding (MBB) of coaxial conductors that extend through the thickness of the various dies. One of the semiconductor chips includes power supply and power conditioning circuitry that is operable to generate multiple operating voltages. The coaxial conductors are selectively connected to ICs housed within the dies so as to provide each IC with an appropriate one of the multiple operating voltages. Digital memory and logic dies are thus interconnected with analog and/or radio frequency (RF) dies, such that digital, analog, and/or RF functions are incorporated in a single package.
Methods of making these circuits and devices, all of which use vertically stacked integrated circuit dies, are also disclosed. Still further and other embodiments, advantages, and aspects of the present invention will become apparent upon reading the following detailed description, and by reference to the drawings.